fix(pcie): PCIe bridge windows to include final BAR

[Sujana-M]

• The common baremetal PCIe enumeration code recorded the final allocated 32-bit BAR base as the resource limit. When the limit matched the allocation cursor, get_resource_base_32() subtracted 1 MiB before programming the Root Port memory window.
• For devices with 1 MiB-aligned endpoint BARs, this caused the Root Port non-prefetchable or prefetchable forwarding window to stop one BAR early.
• Track the inclusive end address for the last allocated 32-bit BAR instead of the BAR base, and stop subtracting BAR_INCREMENT during bridge window programming.
• Also replace the Memory Base/Limit address fields explicitly when updating the Type 1 registers so stale address bits from the previous register value cannot survive.
• Tested with a PCIe hierarchy containing multiple 1 MiB endpoint BARs behind one Root Port. The Root Port NP window now covers the final BAR range.

Change-Id: I75d3085f8c5b64f531c4e8f3f893720c7db1aaa5