feat(minimax_h3): add MPS support, Turbo config and VAE fixes - #1497
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Preserve upstream persistent AdaLN cache and lazy runner construction while retaining MPS query chunking, short clips, and clone-free disk streaming. Adapt cache device selection for MPS and refresh merge regression tests. Validation: 169 tests passed on host MPS; CLI help smoke passed. The uncommitted target-bytes patch remains separately saved in stash.
Preserve SM120 FP8-F16 accumulation alongside MPS streaming and official VAE loading. Defer Triton import until FP8 execution and adapt isolated test fixtures for the new FP8 helpers.
Remove MPS import guards and None kernel placeholders. Bind kernels when their implementation is selected, retaining the existing quantization fallback order and native PyTorch paths.
Restore the regular attention and RoPE imports without MPS exclusion blocks. Load internal Triton dependencies only in the paths that use them. Move SVG's two JIT kernels into kernels/svg.py and reuse the existing SVG2 utility module for its two permutation kernels. Preserve the registry, public wrapper functions, custom-op declarations, and kernel computations. Add a fresh-process regression check for registration without Triton under MPS and CUDA platform settings, native LayerNorm execution, and early failure when constructing Triton MM/Norm implementations without Triton. Validation: 11 tests and pre-commit checks passed. The 512x512, 22-frame, 4-step MPS T2AV output is byte-identical to the previous output, including decoded video/audio. AST comparison confirms unchanged computations in 45 attention classes/functions, including all four relocated kernels. CUDA registration was checked without CUDA hardware; its kernels were not executed on this host.
Resolve PR ModelTC#1497 inference-class selection conflict by retaining upstream DPCache support and the MPS disk-streaming path. Keep feature caching unsupported for disk streaming instead of selecting an incompatible offload backend. Extend inference selection regression coverage for resident, model offload, block offload, and unsupported caching combinations. Validation: 22 MPS streaming/audio VAE regression tests passed; all pre-commit hooks passed; MPS CLI help smoke passed.
Keep the common launch script unchanged from upstream. Let the MPS entry point invoke the Python cache builder directly while retaining its model, configuration, interpreter and argument overrides. Update the MPS usage notes. Validation: bash syntax checks, MPS cache CLI help smoke from outside the repository with PYTHONPATH unset, and pre-commit checks for the changed files passed.
Add commented Apple Silicon MPS environment settings alongside the existing platform examples. Document matching the cache configuration to inference. Default CUDA commands remain unchanged.
The AdaLN builder explicitly uses FP32 for the time MLP and BF16 for modulation projections, so the platform example only needs PLATFORM=mps.
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Summary
This PR adds MPS support for MiniMax-H3 inference in LightX2V and fixes several compatibility issues found during validation on Apple Silicon.
Main changes
Validation
Tested on MacBook with Apple Silicon:
All related tests pass.
Notes
The changes mainly target Apple Silicon / MPS compatibility while preserving existing CUDA behavior.