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Connect six core modules through PC, operand, writeback, branch, and jump paths with guarded little-endian instruction fetch, configurable assembler image loading, missing-image diagnostics, and strict top lint.
Add a four-cycle SystemVerilog smoke test with a sparse NOP image, configurable VCD output, and completion reporting; clarify instruction-image initialization in top.
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Connect six core modules through PC, operand, writeback, branch, and jump paths with guarded little-endian instruction fetch, configurable assembler image loading, missing-image diagnostics, and strict top lint.