Issues

• invalid escape sequence '\s'

  PyHDI/Pyverilog#140 · Filter by author 0BananaBig0 opened on Aug 12, 2026

• Race condition in vparser.parser.parse during multi-processing due to static preprocess_output filename

  PyHDI/Pyverilog#139 · Filter by author Hinataee opened on Jan 14, 2026

• Lack metod ‘visit_Sla’ in ASTCodeGenerator to generate SLA operator

  PyHDI/Pyverilog#138 · Filter by author Hinataee opened on Jan 14, 2026

• casez can not be reverted to code well

  PyHDI/Pyverilog#137 · Filter by author Hinataee opened on Jan 12, 2026

• Bug: ports mentioned in verilog file are taken as declaration.

  PyHDI/Pyverilog#135 · Filter by author rahultanwar10 opened on Jan 30, 2025

• Request: Add generated API documentation for this library

  PyHDI/Pyverilog#134 · Filter by author parker-research opened on Nov 28, 2024

• Feature Request: Add strong typing to this library

  PyHDI/Pyverilog#133 · Filter by author parker-research opened on Nov 28, 2024

• TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py

  PyHDI/Pyverilog#131 · Filter by author zhangshuaiAA9 opened on Jul 13, 2024
  2

• ANSI Style localparam causes parsing error

  PyHDI/Pyverilog#129 · Filter by author mclark-iontra opened on Jun 15, 2024

• Codegen arrays

  PyHDI/Pyverilog#128 · Filter by author CapucinedeBoissac opened on Oct 30, 2023

• Unsized numbers without base solution

  PyHDI/Pyverilog#127 · Filter by author YSJL opened on Oct 30, 2023

• parser error

  PyHDI/Pyverilog#126 · Filter by author 1353369570 opened on Oct 20, 2023

• Attribute error in parser

  PyHDI/Pyverilog#125 · Filter by author KatCe opened on Oct 15, 2023

• Parse Error: Cannot parse a function

  PyHDI/Pyverilog#124 · Filter by author KatCe opened on Oct 15, 2023
  1

• AST node

  PyHDI/Pyverilog#122 · Filter by author lijiale6224 opened on Oct 5, 2023
  1

• Can not support "generate case" statement

  PyHDI/Pyverilog#121 · Filter by author TonyLiaoZP opened on Jun 3, 2023

• unsufficient parse for large scale verilog design

  PyHDI/Pyverilog#118 · Filter by author ZhaoYunfei123 opened on Mar 14, 2023

• TypeError: generate() got an unexpected keyword argument 'reorder'

  PyHDI/Pyverilog#117 · Filter by author Sanjaya97 opened on Feb 22, 2023
  3

• Unsized numbers without base not supported

  PyHDI/Pyverilog#116 · Filter by author Louis-DR opened on Feb 19, 2023
  2

• Specify statements

  PyHDI/Pyverilog#115 · Filter by author lilasrahis opened on Feb 2, 2023
  1

• Parsing Issues

  PyHDI/Pyverilog#114 · Filter by author kwmartin opened on Oct 27, 2022
  1

• ParseError for User Defined Primitives

  wontfix
  PyHDI/Pyverilog#113 · Filter by author TheMatt2 opened on Oct 25, 2022
  1

• Parser Error for resettable D Flip-Flop

  PyHDI/Pyverilog#112 · Filter by author kwmartin opened on Oct 11, 2022
  1

• Parse Error for Inverter Gate

  PyHDI/Pyverilog#111 · Filter by author kwmartin opened on Oct 11, 2022

• Parsing Error for integer memories

  PyHDI/Pyverilog#110 · Filter by author kwmartin opened on Sep 19, 2022