[0z5a]

InjectPTXAsyncCopy can lower a 16-byte copy to cp.async even when the source or destination address is not provably 16-byte aligned. Check declared buffer alignment and symbolic offsets before injecting the instruction; preserve the original store otherwise. The check accounts for the byte buffer used by merged dynamic shared memory.

Fixes #20912.

Testing

• Six focused IR regression cases passed with this change alone, covering aligned addresses, unaligned source/destination row strides, and insufficient base alignment.
• Existing aligned scalar, vector, and merged-shared-memory CPU lowering checks continued to inject the expected instructions.
• On GH200, aligned and unaligned numerical cases passed with this change together with an experimental TIRx scalar-store fallback and the separate non-unit-stride fix. That is combined testing, not a standalone GPU result for this PR.

The current pinned TIRx may reject an unaligned vector store after the fallback rather than compile it; this PR prevents emitting an unsafe async copy, while a scalar-store fallback is a separate follow-up.