Hardware Prefetch Tuning for E-Cores by IntelSwede · Pull Request #41 · intel/optimization-zone

IntelSwede · 2026-07-02T15:11:34Z

No description provided.

rsiyer-intel · 2026-07-07T23:25:12Z

+
+Prefetches can be scrubbed by throttlers prior to being accepted. These throttlers are designed to reduce a combined high prefetch level within the module as well as reducing the prefetch requests when the Uncore memory subsystem is at a high load.
+
+<div id="figure-1" style="display:flex; flex-direction: column;justify-content: center; align-items: center; margin: 20px auto">


Likely broken image link -
For images, please create an images folder, add the image and link it, similar to these recipes-
https://github.com/intel/optimization-zone/tree/main/software/kafka/images
https://github.com/intel/optimization-zone/tree/main/software/mysql-postgresql/images

In the main readme , can link it using relative path

![alt text](images/image-1.png) ![alt text](images/image-2.png) ![alt text](images/computemodule.png)

rsiyer-intel

Please review and fix these -

Typos -

Prefetecher → Prefetcher
hardware/HWPrefetchTuning/README.md:145
LCC Streamer → LLC Streamer
hardware/HWPrefetchTuning/README.md:187
This even counts → This event counts
hardware/HWPrefetchTuning/README.md:346
on figurable → probably configurable
hardware/HWPrefetchTuning/README.md:388
There are two types if enable bits → probably There are two types of enable bits
hardware/HWPrefetchTuning/README.md:251
Likely formatting / numbering / anchor mistakes

TOC item missing period:

1.3.4 [L2 Next Line Prefetch (L2 NLP)] should probably be 1.3.4. ...
hardware/HWPrefetchTuning/README.md:39

Update references to Section 0 to appropriate Section 4.4
hardware/HWPrefetchTuning/README.md:193
hardware/HWPrefetchTuning/README.md:264 (broken link)
hardware/HWPrefetchTuning/README.md:268
hardware/HWPrefetchTuning/README.md:284

Heading level inconsistency:

4.5 MSR 0x1323 should likely be ## 4.5 MSR 0x1323

hardware/HWPrefetchTuning/README.md:532
Support tag typo in table:
GR → probably GRT
hardware/HWPrefetchTuning/README.md:538

Likely wording/grammar issues:
Unless otherwise stated features are forward to later generations.
likely meant something like Unless otherwise stated, features are carried forward to later generations.
hardware/HWPrefetchTuning/README.md:120

The CORE_TYPE set to 0x20...
likely missing "is"
hardware/HWPrefetchTuning/README.md:121

Setting the disable freezes...
likely Setting this bit disables... or Setting the disable bit freezes...
hardware/HWPrefetchTuning/README.md:296

increased and decrease in performance
likely increases and decreases in performance
hardware/HWPrefetchTuning/README.md:300

Possible terminology inconsistencies

DCU Next Page Prefetcher (L1 NLP) seems inconsistent; should probably be L1 NPP
hardware/HWPrefetchTuning/README.md:235

Demand throttler (DPT) looks inconsistent with earlier Demand Throttling of Prefetches (DTP)
hardware/HWPrefetchTuning/README.md:246

harp-intel

Valuable content. Thanks for submitting. A few items noted.

harp-intel · 2026-07-08T15:56:09Z

repo convention is to put images in 'images' subdirectory. Please create subdirectory and move this image into it. Update any links.

harp-intel · 2026-07-08T16:03:38Z

As this content is specific to E-core prefetchers, directory should be renamed, e.g., ecorePrefetchTuning.

harp-intel · 2026-07-08T16:04:26Z

Link to this document should be added to root README.md TOC.

harp-intel · 2026-07-08T16:12:38Z

+
+# 3 PERFORMANCE MONITORS
+
+Performance monitoring events in the Intel® E-core are relevant to hardware prefetch tuning as they allow for tracking of increased and decrease in performance as well as execution behavior changes. See the respective device manual for details. Performance events are also available at [perfmon-events.intel.com](perfmon-events.intel.com). Core events can either be specified through the event/umask combination or by using PMU tools such as Intel® vTune™ or Perf in Linux. For example, the following Linux command can be used to measure cycles, instructions and cycles spent on the oldest load for core 0 during 1 seconds:


Link to external site needs protocol (https://) otherwise interpreted as relative link.

adgubrud · 2026-07-15T15:30:43Z

+
+# 1 INTRODUCTION
+
+Hardware prefetchers are an excellent way of improving performance by fetching information ahead of time. The most basic prefetchers that only fetched the next cache line were introduced in the early days of processors. Today, prefetchers can track complex patterns to get the most relevant data into the caches ahead of usage. However, prefetching in multicore systems is a complex task; it can improve performance significantly, but driving more data into the caches can also evict more relevant data. Furthermore, prefetchers drive up the DDR bandwidth, which can become a bottleneck and lower overall system performance. By tuning the prefetchers, one can ensure optimal performance at any given time.


Suggested change

Hardware prefetchers are an excellent way of improving performance by fetching information ahead of time. The most basic prefetchers that only fetched the next cache line were introduced in the early days of processors. Today, prefetchers can track complex patterns to get the most relevant data into the caches ahead of usage. However, prefetching in multicore systems is a complex task; it can improve performance significantly, but driving more data into the caches can also evict more relevant data. Furthermore, prefetchers drive up the DDR bandwidth, which can become a bottleneck and lower overall system performance. By tuning the prefetchers, one can ensure optimal performance at any given time.

Hardware prefetchers are an excellent way of improving performance by fetching information ahead of time. The most basic prefetchers that only fetch the next cache line were introduced in the early days of processors. Today, prefetchers can track complex patterns to get the most relevant data into the caches ahead of usage. However, prefetching in multicore systems is a complex task. It can improve performance significantly, but driving more data into the caches can also evict more relevant data. Furthermore, prefetchers drive up the DDR bandwidth, which can become a bottleneck and lower overall system performance. By tuning the prefetchers, one can ensure optimal performance at any given time.

adgubrud · 2026-07-15T15:35:25Z

+
+### 1.2.2 NEXT LINE PREFETCHER (L1 NLP)
+
+The NLP is commonly referred to as the DCU Stream Prefetecher.


Suggested change

The NLP is commonly referred to as the DCU Stream Prefetecher.

The NLP is commonly referred to as the DCU Stream Prefetcher.

adgubrud · 2026-07-15T15:37:37Z

+
+#### LOAD_HIT_PREFETCH.HWPF
+
+This event counts the number of demand loads that hit an outstanding L1 prefetch in the request buffers that could result in an L2 cache hit or miss. This is a good indicator that the prefetch request was initiated too closely to the demand and was not completed in time to get the full benefit of prefetching. Similar indications as the XQ_PROMOTION events for L2 cache misses.


Suggested change

This event counts the number of demand loads that hit an outstanding L1 prefetch in the request buffers that could result in an L2 cache hit or miss. This is a good indicator that the prefetch request was initiated too closely to the demand and was not completed in time to get the full benefit of prefetching. Similar indications as the XQ_PROMOTION events for L2 cache misses.

This event counts the number of demand loads that hit an outstanding L1 prefetch in the request buffers that could result in an L2 cache hit or miss. This is a good indicator that the prefetch request was initiated too close to the demand and was not completed in time to get the full benefit of prefetching. Similar indications as the XQ_PROMOTION events for L2 cache misses.

adgubrud · 2026-07-15T15:39:37Z

+
+#### IMC RD/WR CAS
+
+The Integrated Memory Controller (IMC) on client platforms typically has two static counters tracking the number of read and write requests. On server platforms, there are generally on figurable performance monitoring counters instead. These counters measure requests per cache line, so the value should be multiplied by 64 to get the number of bytes transferred. The static counters start counting on power-on, and the configurable counters start counting when the start signal is provided. In either case, the amount of DDR requests generated is derived by taking the delta values between two points in time.


Suggested change

The Integrated Memory Controller (IMC) on client platforms typically has two static counters tracking the number of read and write requests. On server platforms, there are generally on figurable performance monitoring counters instead. These counters measure requests per cache line, so the value should be multiplied by 64 to get the number of bytes transferred. The static counters start counting on power-on, and the configurable counters start counting when the start signal is provided. In either case, the amount of DDR requests generated is derived by taking the delta values between two points in time.

The Integrated Memory Controller (IMC) on client platforms typically has two static counters tracking the number of read and write requests. On server platforms, they are generally found on configurable performance monitoring counters instead. These counters measure requests per cache line, so the value should be multiplied by 64 to get the number of bytes transferred. The static counters start counting on power-on, and the configurable counters start counting when the start signal is provided. In either case, the amount of DDR requests generated is derived by taking the delta values between two points in time.

adgubrud · 2026-07-15T15:46:00Z

+| LLC or L3 cache  | Platform cache, located outside of core module                                 |
+|                  |                                                                                |
+
+This document covers multiple E-core microarchitectures. Unless otherwise stated features are forward to later generations.


This wording is a bit unclear. Can you please rewrite the second sentence here? Are you saying that unless otherwise stated there is support for a given feature from Gracemont onward?

adgubrud · 2026-07-15T16:46:53Z

+|   GRT   |   1   | 45:45 | Begin tracking requests coming from the L1 NPP prefetcher. Affects both the MLC Stream and AMP.          |
+|   GRT   |   1   | 46:46 | Begin tracking requests coming from the L1 IPP prefetcher. Affects both the MLC Stream and AMP.          |
+|   GRT   |   1   | 47:47 | Allow NPP prefetcher to train L2 prefetchers.                                                            |
+|   GRT   |   1   | 48:48 | Allow IPP prefetcher to train L2 prefetchers.                                                            |


Setting to 1 enables attribute?

adgubrud · 2026-07-15T16:47:22Z

+| Support | Width | Bits  | Descriptor                                                                                                                                           |
+| :-----: | :---: | :---: | :--------------------------------------------------------------------------------------------------------------------------------------------------- |
+|   CMT   |   5   |  4:0  | Maximum size of L2 Stream prefetcher window that a demand can hit and keep the prefetcher going. A larger window gives more aggressive prefetching   |
+|   CMT   |   1   |  5:5  | Enabled kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page                            |


Setting to 1 enables attribute?

adgubrud · 2026-07-15T16:47:29Z

+| Support | Width | Bits  | Descriptor                                                                                                                                           |
+| :-----: | :---: | :---: | :--------------------------------------------------------------------------------------------------------------------------------------------------- |
+|   CMT   |   5   |  4:0  | Maximum size of L2 Stream prefetcher window that a demand can hit and keep the prefetcher going. A larger window gives more aggressive prefetching   |
+|   CMT   |   1   |  5:5  | Enabled kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page                            |


Suggested change

| CMT | 1 | 5:5 | Enabled kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page |

| CMT | 1 | 5:5 | Enables kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page |

adgubrud · 2026-07-15T16:49:03Z

+|   CMT   |   1   | 43:43 | LLC Stream disabled; when set to 1, the LLC Streamer is disabled.                                                                                           |
+|   CMT   |   3   | 46:44 | Sets the number of LLC Streamer prefetches to be sent when a prefetch stream is established.                                                                |
+|   CMT   |   5   | 51:47 | Sets the maximum number of LLC Streamer prefetches that can be queued.                                                                                      |
+|   CMT   |   5   | 57:53 | LLC Stream LQ threshold. Specifies the minimum number of empty LQ entries required to emit prefetches. Higher values result in fewer LLC Stream prefetches. |


XQ is defined earlier in the document, but what is LLC Stream LQ?

adgubrud · 2026-07-15T16:50:26Z

+|   CMT   |   3   | 19:17 | Throttle level for negative lower quartile value for the reuse throttle counter. Negative quartile implies less reuse of prefetched lines. 3=highest, 0=lowest |
+|   CMT   |   3   | 22:20 | Throttle level for negative upper quartile value for the reuse throttle counter. Negative quartile implies less reuse of prefetched lines. 3=highest, 0=lowest |
+|   CMT   |   3   | 25:23 | Throttle level for negative saturation value for the reuse throttle counter. Negative saturation implies least reuse of prefetched lines. 3=highest, 0=lowest  |
+|   CMT   |   1   | 26:26 | Turns on L2 prefetcher throttling based on reuse metrics                                                                                                       |


Setting to 1 enables attribute?

Hardware Prefetch Tuning for E-Cores

8df4c38

rsiyer-intel reviewed Jul 7, 2026

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rsiyer-intel requested changes Jul 7, 2026

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harp-intel requested changes Jul 8, 2026

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adgubrud self-requested a review July 15, 2026 15:24

adgubrud requested changes Jul 15, 2026

View reviewed changes


		Prefetches can be scrubbed by throttlers prior to being accepted. These throttlers are designed to reduce a combined high prefetch level within the module as well as reducing the prefetch requests when the Uncore memory subsystem is at a high load.

		<div id="figure-1" style="display:flex; flex-direction: column;justify-content: center; align-items: center; margin: 20px auto">


		# 3 PERFORMANCE MONITORS

		Performance monitoring events in the Intel® E-core are relevant to hardware prefetch tuning as they allow for tracking of increased and decrease in performance as well as execution behavior changes. See the respective device manual for details. Performance events are also available at [perfmon-events.intel.com](perfmon-events.intel.com). Core events can either be specified through the event/umask combination or by using PMU tools such as Intel® vTune™ or Perf in Linux. For example, the following Linux command can be used to measure cycles, instructions and cycles spent on the oldest load for core 0 during 1 seconds:


		# 1 INTRODUCTION

		Hardware prefetchers are an excellent way of improving performance by fetching information ahead of time. The most basic prefetchers that only fetched the next cache line were introduced in the early days of processors. Today, prefetchers can track complex patterns to get the most relevant data into the caches ahead of usage. However, prefetching in multicore systems is a complex task; it can improve performance significantly, but driving more data into the caches can also evict more relevant data. Furthermore, prefetchers drive up the DDR bandwidth, which can become a bottleneck and lower overall system performance. By tuning the prefetchers, one can ensure optimal performance at any given time.


		### 1.2.2 NEXT LINE PREFETCHER (L1 NLP)

		The NLP is commonly referred to as the DCU Stream Prefetecher.


		#### LOAD_HIT_PREFETCH.HWPF

		This event counts the number of demand loads that hit an outstanding L1 prefetch in the request buffers that could result in an L2 cache hit or miss. This is a good indicator that the prefetch request was initiated too closely to the demand and was not completed in time to get the full benefit of prefetching. Similar indications as the XQ_PROMOTION events for L2 cache misses.


		#### IMC RD/WR CAS

		The Integrated Memory Controller (IMC) on client platforms typically has two static counters tracking the number of read and write requests. On server platforms, there are generally on figurable performance monitoring counters instead. These counters measure requests per cache line, so the value should be multiplied by 64 to get the number of bytes transferred. The static counters start counting on power-on, and the configurable counters start counting when the start signal is provided. In either case, the amount of DDR requests generated is derived by taking the delta values between two points in time.

	\| CMT \| 1 \| 5:5 \| Enabled kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page \|
	\| CMT \| 1 \| 5:5 \| Enables kick-start for L2 Stream prefetcher. This is used when an access is detected at the beginning or end of a 4K page \|

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IntelSwede commented Jul 2, 2026

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rsiyer-intel left a comment

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4.5 MSR 0x1323 should likely be ## 4.5 MSR 0x1323

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