add entries for ARM Cortex-A720 + A750 CPUs - #4091
Merged
Merged
Conversation
Per-CPU raw event types were introduced for x86 hybrid CPUs, but the unconditional assignment also replaced the sentinel used by named AArch64 PMUs. Only substitute configurations that actually use PERF_TYPE_RAW so architecture-specific post-processing can resolve named PMUs. Fixes rr-debugger#4072.
Separate PMU eligibility from the existing P-core preference. Automatic 'any' selection now considers every supported CPU, while default selection additionally prefers P-cores. Explicit numeric CPU binding remains unchanged.
Recognize Cortex-A520 and Cortex-A720 MIDRs. Enable deterministic BR_RETIRED and STREX_SPEC counting on A720 with a measured skid of 1000. Keep A520 unsupported because its retired-branch counter intermittently overcounts.
Collaborator
|
Looks great, thanks!! |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR adds support for Cortex-A720 cores, marks the Cortex-A520 as unsupported, and possibly fixes the regression noted in #4072
I tested out
rron an MS-R1 box which has a CIX P1 chip, which has both Cortex-A720 and Cortex-A520 cores. The Cortex-A720 PMU passed all tests, and the Cortex-A520 PMU intermittently overcounted branches so it's marked unsupported.While doing the validation, I found two additional places that needed small tweaks:
Preserving named PMU event types -- this change in
PerfCounters.ccI think fixes the regression noted in rr should open all PMUs #4072 where AArch64 systems with heterogeneous cores could result in seeing no branch eventsUpdate automatic CPU selection -- the existing logic could result in a A520 core being selected. I've updated the selection code to first filter for only supported CPUs (and then filter to P cores if available as before).
I've read the contributor guidelines, but admittedly this is my first commit here. Happy to make any changes necessary, and thanks for the great project 🙇